1. Field of the Invention
The invention generally relates to the field of integrated circuit design performance analysis and optimization, and particularly to the delay and crosstalk noise calculation for logic cells used in statistical static timing analysis of digital integrated circuit.
2. Description of the Related Art
In modern very large-scale integrated circuit (VLSI) design, it is very important to improve the circuit operating speed and to verify if the circuit can perform at a target frequency. To achieve these goals, circuit designers extensively use timing verification and optimization software from Electronic Design Automation (EDA) vendors on their designs. Two main methodologies for timing verification are used: 1) transistor-level simulation based method and 2) cell/gate-level static timing analysis. The transistor-level simulation method can accurately simulate the circuit timing behavior, but this method is very time-consuming and is not feasible for a full-chip analysis. Static timing analysis provides a fast method to estimate circuit timing performance, and can be used for full-chip analysis.
In VLSI digital circuits, logic cells are the basic building blocks; logic cells are interconnected with metal wires. In static timing analysis, logic cell delay models are becoming more and more complicated as semiconductor technologies evolve. Prior to the 1980s, cell delays could be modeled as a constant number. During the 1980s, CMOS technologies were widely used, and cell delays became a function of input transition time and load capacitance. Early in the 1990's, due to interconnect scaling, logic cell delays became a function of gate and RC (resistance capacitance) interconnect loading. In the early 2000s, the increased thickness of metal wire (relative to the feature size) has resulted in strong coupling capacitance between different interconnects; and logic cell delay has become a function of coupling interconnect (i.e., crosstalk).
Moreover, the further decrease in feature sizes for nanoscale CMOS technologies increases the importance of process variations. These variations introduce uncertainty in circuit behaviors and significantly impact the circuit performance and product yield. The increased variability has given a new set of problems for circuit timing analysis. However, current delay calculation methods do not handle process and environmental variations from both cells and interconnects. The corner-based methodology for worst-case analysis traditionally used in static timing analysis may be overly pessimistic as well as extremely inaccurate. A better circuit timing methodology is needed to more accurately account for circuit behavior as it is influenced by process variations.
Attempts to solve the statistical timing analysis problem can be largely be categorized as being in one of two approaches: either a path-based approach or a block-based approach. (See J. A. G. Jess and K. Kalafala et al, “Statistical timing for parametric yield prediction of digital integrated circuits”, Design Automation Conference (DAC), pp. 932-937, June 2003; H. Chang and S. S. Sapatnekar, “Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-like Transversal”, ICCAD 2003, pp. 621-625, November 2003; Aseem Agarwal, David Blaauw, Vladimir Zolotov and Sarma B. K. Vrudhula, “Statistical Timing Analysis Using Bounds”, DATE 2003, pp. 10062-10067; Anirudh Devgan and Chandramouli Kashyap, “Block-based Static Timing Analysis with Uncertainty”, ICCAD 2003, November 2003; Jiayong Le, Xin Li and L. Pileggi, “STAC: statistical timing analysis with correlation,” IEEE Design Automation Conference, 2004).
However, both path based and block based approaches focus not on delay calculation but on high level timing propagation problems wherein the delay is assumed (based on a simple model) rather than calculated. With the decreasing of feature size in semiconductor technology, statistical cell delay can no longer be modeled as a simple value or function. The non-linear input waveform, the metal interconnect resistiveness, and non-linear receiver capacitance all have strong effects on cell delay. While some of these factors are accounted for in nominal delay calculation techniques, other factors have yet to be modeled. Process variations cause these factors to have statistical distributions. Consequently, all nominal delay calculation approaches (such as, for example, the effective capacitance method) are not currently able to capture statistical information accurately. A statistical delay calculation methodology is needed for greater accuracy in statistical timing analysis.
Crosstalk between nanoscale size features also complicates statistical timing analysis. At nanoscale feature sizes, the dominant portion of wiring capacitance is the inter-layer neighboring wire capacitance. Consequently, the delay of a gate can be greatly impacted by the switching activity on neighboring wires (see R. Arunachalam, K. Rajagopal and L. Pileggi, TACO: Timing Analysis with Coupling” Proceedings of the Design Automation Conference, pp. 266-269, June 2000). Accounting for this cross-talk effect, therefore, is a critical part of the statistical timing analysis process.
The “crosstalk effect” becomes significant when the coupling capacitance between adjacent interconnects increases. A coupled interconnect system includes a victim net and several aggressor nets. For a good discussion of coupled interconnect systems, see R. Arunachalam, K. Rajagopal and L. Pileggi, TACO: Timing Analysis with Coupling” Proceedings of the Design Automation Conference, pp. 266-269, June 2000—which is incorporated by reference as if fully set forth herein. A net is a set of nodes resistively connected. A net has one driver node, one or more fanout nodes, and may have a number of intermediate nodes that are part of the interconnect. “Fanout” is the ability of a logic gate to drive further logic gates; fanout refers to or is quantified by referring to the number of gates before voltage falloff causes errors.
An “aggressor net” is a net that has significant coupling capacitance to the victim net so as to be able to influence the delay of the victim gate. A gate is a logic unit or cell. Each net has its ground capacitances, and there are coupling capacitances between different nets. When circuit feature size decreases, the space between interconnects is reduced and the ratio of coupling capacitance and substrate capacitance increases proportionally.
The effects of crosstalk (“crosstalk effect”) pose two major problems. In the case where the victim net is quiet (non-switching), capacitive crosstalk can induce noise (glitches) and potentially cause functional failures. For example, if a glitch happens when the clock signal of a register is switching, the data in the register may be flipped accidentally. Alternatively, in a case where the victim net is active, crosstalk can change the delay of the victim if the aggressor is also switching. If the aggressor is switching in the opposite direction, crosstalk can lead to an increase in delay, which may cause “setup time violations.” If the aggressor is switching in the same direction as the victim, crosstalk may lead to the delay decreasing, and may cause “hold time violations.”
What is needed is a method of statistical timing that accounts for crosstalk as well as accounting for cell delay and noise.